Over the last few decades, electronic design automation (EDA) has emerged as an efficient and reliable alternative to the expensive and cumbersome process of fabricating and testing of high speed electronic circuits. A major area of focus for the EDA community is the accurate characterization of high speed distributed networks such as interconnects and power distribution networks (PDNs) commonly found at all hierarchical levels of integration. Currently rapid simulation of such structures suffer from two main challenges. Firstly, with the sustained increase in frequency of operation and 3-D integration, system models of such structures are extremely massive rendering the classical direct EDA techniques to be prohibitively slow. Moreover, modern computing systems have evolved from single processor machines to multi-core/multi-processor and high performance computing (HPC) systems. This paradigm shift in computing systems has meant that traditional sequential EDA algorithms are no longer compatible with modern hardware and hence, the current state-of-art in EDA needs to migrate towards parallel alternatives. My presentation will consider possible parallel EDA algorithms, the current limitations of such algorithms and ground breaking research that will, within the next 5 years revolutionize the future of parallel EDA algorithms.

Speaker(s): Sourajeet Roy,

Agenda:
6:30-7:30 pm presentation by prof Roy

Location:
Room: 603
Bldg: 3480 University St.
McConnell Engineering Building
Montreal, Quebec