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DL Seminar: Basics of Jitter in Wireline Communications

November 4, 2019 @ 2:00 pm - 3:30 pm EST

Jitter refers to deviation from ideal timing in clock and data transitions. In wireline communications, jitter reduces the timing margin available for clock and data recovery (CDR) circuits and poses significant challenges to signal integrity as the data rates march towards 64Gb/s/lane and beyond. In this talk, we first review the basic definitions of jitter and its properties, and the effects of jitter on CDR and other building blocks of a wireline system. We then describe the methods of characterizing, modeling, and simulating jitter. Finally, we present some recent works on jitter measurement and jitter mitigation techniques that are used to optimize the link performance.

Speaker(s): Professor Ali Sheikholeslami,

Room: 1.162
Bldg: EV (Engineering and Visual Arts Building)
1515 Ste-Catherine West
Montreal, Quebec


November 4, 2019
2:00 pm - 3:30 pm UTC