While for a long time the capabilities of digital systems have been increasing exponentially according to Moore’s famous prediction, this continued progression is now hampered by the difficulty of reducing the energy consumption of CMOS circuits. A possible approach to improve energy efficiency consists in bringing the supply voltage closer to the threshold voltage. However, this increases the circuit’s sensitivity to variations, and in a conventional synchronous system, forces the use of large safety margins to ensure the reliable operation of the system. The requirement that circuits should be reliable is therefore a major impediment to increased energy efficiency. In this talk, we discuss the design of quasi-synchronous systems, which allow some timing violations to occur to decrease energy consumption, while preserving a desired performance level. This approach is particularly suited to signal processing systems that include a form of redundancy, such as error-correction decoders. We focus on the case of an LDPC decoder, and show how the impact of circuit faults can be modeled accurately, and present a low-complexity method to find operating conditions for the circuit that minimize energy subject to performance constraints.

Speaker(s): François Leduc-Primeau,

Location:
Room: M-2101
Bldg: Polytechnique Montréal, Pavillon Lassonde
Montreal, Quebec